Integrated circuits based on complementary metal-oxide semiconductor (CMOS) transistor technology are widely used in modern electronic systems. The proper performance of CMOS integrated circuits is often critically dependent on the stable operation of its MOS transistors. Even relatively small changes in transistor performance can have a strong impact on the operation of sensitive circuitry on a high performance CMOS chip.
The operation of a transistor can be significantly affected by changes in the transistor's threshold voltage due to aging induced by hot carrier, which is also referred to as CHC (channel hot carrier), and Negative Bias Temperature Instability (NBTI). High performance PMOS transistors exhibit instability after voltage/temperature aging. This phenomenon is known as NBTI. The instability occurs under negative gate voltage and is measured as an increase in the magnitude of threshold voltage. Higher stress temperatures produce more degradation. Hot carrier, on the other hand, is a degradation phenomenon, more prominent in nMOS transistors, wherein the performance of the nMOS transistor degrades due to injection of hot carriers into the gate oxide. This manifests itself in degrading the transistor threshold voltages and mobility, which can eventually lead to reduction of the drive current, ION.
If a transistor's threshold voltage increases even slightly, the transistor's ability to drive current may be reduced sufficiently that a sensitive digital logic circuit in which the transistor is operating will slow down substantially or no longer function properly and the gain of certain sensitive analog circuits may be degraded. This can disrupt the proper functioning of the entire integrated circuit.
CMOS integrated circuits contain p-channel (PMOS) and n-channel (NMOS) transistors. The threshold voltage of a PMOS transistor can change over time due to NBTI instability induced aging. NBTI arises when MOS devices are exposed to negative gate bias voltages under elevated operating temperatures, i.e., the input of CMOS inverter is held at logic ‘low’. Threshold voltage increases due to NBTI may be significant, i.e., on the order of tens of millivolts over the lifetime of a circuit. The threshold voltages in NMOS transistors may also increase over time due to the accumulation of gate-oxide change from hot carrier effects, known as CHC; this happens when the transistors are conducting current—typically when the transistors are switching their states in a digital integrated circuit or the pass gates like scenarios in analog circuits. Generally, NBTI induced aging affects PMOS pull-up performance and CHC related aging degrades NMOS pull-down performance.
Traditional way to deal with transistor performance degradation phenomenon at the design level is through margining. This involves making bounding predictions on the performance of the integrated circuit by estimating the extent to which a representative transistor can degrade under certain operating conditions.
The current techniques assess the reliability kinetics of a circuit to estimate the product performance drift after a stipulated lifetime at a defined set of stress voltage and temperature. The term “product performance drift” refers to deterioration in a circuit operating frequency due to transistor slow-down induced by aging. The product performance drift can also manifest in increasing the delay of the critical path in a chip and hence can result in leading to functional failures. The reliability kinetics is obtain by either performing reliability simulations in a BERT (Berkeley Reliability Tools) like framework, wherein the product lifetime, operating voltage and temperature are fed in the simulator to get the performance drift as an output, or by performing silicon level measurements that uses targeted design of experiments at accelerated stress conditions to output an empirically or physically based mean reliability model as a function of time and stress parameters.
The above technique is a default choice for many designers due to lack of techniques which can reduce aging, except for a few techniques that are employed at transistor level for alleviating hot carrier degradation to a certain extent. This includes increasing the channel length of the nMOS device or stacking it with another device; both of these, however, can come with penalties—either in area or in performance.
One current technique solves the problem at design level by increasing VDD (headroom) by tracking aging of the reference circuit to recover the lost performance. However, this technique does not provide an individual handle on a PMOS device. Further, this technique applies the same increased operating voltage VDD to both PMOS and NMOS transistors in the integrated circuit even though they degrade at different rates due to aging, which can significantly affect the integrated circuit properties by skewing the beta ratio. Furthermore, increasing operating voltage VDD can result in further performance degradation as it is one primary reason for degradation of circuits. Hence, an increment in VDD over the lifetime also risks an accelerated aging of the integrated circuit. In addition, it also poses an increase in leakage power over the circuit lifetime.
Another technique requires using redundant circuitry to counter the effects of aging on the threshold voltage. Such compensation schemes are costly in terms of the area and also generally do not guarantee constant/drift-less performance over the circuit lifetime.
Thus, the existing schemes to determine the impact of hot carrier and NBTI induced aging on the performance of CMOS circuits and to recover the degraded performance are costly and inefficient.